This invention relates to semiconductor memory devices and, more specifically, to electronic circuits and circuit architectures for sensing the stored logic states of memory cells in such semiconductor devices.
There are many types of semiconductor memory devices, such as SRAM (Static Random Access Memory), DRAM (Dynamic Random Access Memory), ROM (Read-Only Memory), NVRAM (Non-Volatile Random Access Memory), etc. In many, if not most, of these semiconductor memory devices, the logic state of a memory cell stored as a bit of data is sensed or “read” by comparing the current of a bit line connected to the data memory cell against the current of a second bit line connected to a reference memory cell. If the current of the bit line connected to the data memory cell is greater than the current of the second bit line connected to the reference memory cell, then the bit stored by the data memory cell is considered to be a particular value, a logic “1,” for example. On the other hand, if the current of the bit line connected to the data memory cell is less than the current of the second bit line connected to the reference memory cell, then the bit stored by the data memory cell is considered to be a logic “0.” The comparison with the reference memory cell allows discrimination between the two logic states to determine the bit stored in the data memory cell. Of course, what is considered logic “1” and “0” is arbitrarily defined.
A problem which has become more apparent is that there is significant variability in the characteristics of the elements of the semiconductor devices with the shrinking dimensions of advanced process technologies. For example, in memory devices both the data memory cells and reference memory cells can have a significant range of operating parameters which can cause problems. If the current output of the reference memory cell is set to close to “0” (assuming “0” corresponds to a low bit line current), noise in the ground plane may cause a false sensing of logic “1” in the data memory cell. But if the reference memory cell is set too high, then a data memory cell with a weak bit line current may cause a false sensing of logic “0” when the current of the data memory cell is compared to the current of the reference memory cell.
Hence there is a need for some sensing technique which is suitable for advanced process technologies and adaptable to the variability of device characteristics.